1. Field of the Invention
The present invention relates to a non-volatile memory device, and more particularly, to an MRAM (Magnetic Random Access Memory).
2. Description of the Background Art
The MRAM is a memory using a magnetic body as a storage element. A phenomenon in which the resistance of a material changes depending on the direction of magnetization of the magnetic body is called an MR (Magneto Resistive) effect. The MR effect is further classified by operating principles. One of such called a TMR (Tunneling Magneto Resistive) phenomenon has been identified as having a high MR ratio (a resistance ratio by magnetization of the magnetic body), and a TMR element has been studied as an element for the MRAM.
The TMR phenomenon is such a phenomenon that the magnitude of tunneling current flowing through an insulation film interposed between magnetic bodies changes in accordance with the direction of electron spin determined by magnetization of the magnetic body.
FIG. 13 schematically shows a conventional thin film having a magnetic tunnel junction (MTJ) at which the TMR phenomenon occurs. The thin film is also referred to as an MTJ element or a tunneling magneto resistive (TMR) element.
Referring to FIG. 13, ferromagnetic films 701, 703 are arranged with an insulation film 702 interposed therebetween. Spin electrons within the magnetic bodies change their state in accordance with the direction of magnetization. Here, if magnetic film 701 has the same direction of magnetization as that of magnetic film 703, the tunneling current increases. By contrast, if the direction of magnetization of magnetic film 701 is opposite to that of magnetic film 703, the tunneling current decreases.
Using such a phenomenon, the direction of magnetization of magnetic film 701 is changed and the magnitude (resistance) of the tunneling current is detected, to allow the TMR element to be used as a storage element. Magnetic film 703 may have the direction of magnetization fixed by an antiferromagnetic body, which is called a spin valve.
In order to realize a high-density non-volatile memory device, memory cells are preferably arranged in a two-dimensional array. A ferromagnetic body has an easily-magnetized direction (low energy state) due to a crystal structure, a shape or the like, the direction being referred to as an easy axis. Magnetization of a storage element is held in a direction along the easy axis. By contrast, a hardly-magnetized direction is called a hard axis.
FIG. 14 shows an asteroid curve for illustrating reversal of magnetization.
Referring to FIG. 14, in order to reverse the direction of magnetization, a magnetic field is applied in a direction opposite to the present magnetization with respect to the easy axis to change the direction of magnetization of a storage element. It is known here that, if a magnetic field is applied in the direction of the hard axis, the direction of magnetization is reversed with a smaller magnetic filed in the direction of the easy axis compared to the case where no magnetic field applied in the direction of the hard axis. The asteroid curve shown in FIG. 14 illustrates the relationship between the magnitude of the magnetic field and the threshold for the reversal of magnetization in the directions of the easy axis and the hard axis.
FIG. 15 shows a two-dimensional arrangement of memory cells in the MRAM.
Referring to FIG. 15, a plurality of interconnection lines 801 are arranged orthogonal to a plurality of interconnection lines 802 arranged parallel to the X-axis. At each intersection of interconnection lines 801 and 802, a magnetic body 803 is interposed between interconnection lines 801 and 802.
If current is provided for a specific line selected from the lines in the X- and Y-directions, magnetization of magnetic body 803 is reversed only in memory cells located at intersections to which a magnetic filed is applied both in the hard and easy axis directions, allowing data rewriting. No magnetic filed exceeding the threshold value is applied to magnetic bodies in the other numerous memory cells, so that no rewriting occurs. Accordingly, writing to the two-dimensional memory array can be realized.
Data reading can be detected by, for example, a method of comparing tunneling current flowing in magnetic body 803 with a reference cell.
FIG. 16 schematically shows a conventional MRAM memory cell (for example, disclosed in the document by Roy, et al., which will be described later).
Referring to FIG. 16, a TMR element 852 in a spin valve form is used as a storage element of a memory cell. A transistor 855 is used as a switch element for reading.
As interconnection lines for transmitting signals, a bit line 851 used at the time of reading and writing, a word line 854 rendering transistor 855 conductive at reading, a digit line 853 providing current at writing, and a source line connected to the source of a transistor (not shown) are provided.
At writing, current is applied to digit line 853 and bit line 851 to generate a synthetic magnetic field at a cell position of interest so as to control the direction of magnetization of a magnetic body in the TMR element.
At reading, voltage is applied to word line 854, rendering transistor 855 conductive. Current is provided from bit line 851 to the source line via TMR element 852 and transistor 855. Here, the magnitude of the flowing current varies depending on the direction of spinning of the TMR element. This current is compared with the current flowing in the reference cell to determine that the data stored in the TMR element is either a logic high of xe2x80x9cHxe2x80x9d or a logic low of xe2x80x9cL.xe2x80x9d Current flowing at the time of reading is considerably lower than the current flowing at the time of writing. Thus, data reading would not apply a magnetic field exceeding the threshold to the TMR element, so that the direction of magnetization of the magnetic body remains unchanged. Hence, the MRAM is capable of nondestructive read out.
It is noted that technical information for the MRAM are disclosed in the documents as follows:
Roy Scheuerlein, et al., xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell,xe2x80x9d ISSCC Digest of Technical Papers, February 2000, TA7.2;
M. Durlam, et al., xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elements,xe2x80x9d ISSCC Digest of Technical Papers, February 2000, TA7.3, pp. 130-131;
U.S. Pat. No. 6,269,040 (FIG. 4A); and
U.S. Pat. No. 6,317,376.
In the MRAM, determination of data is performed by comparing a reference signal with a signal from a memory cell to be read out. U.S. Pat. No. 6,269,040 and U.S. Pat. No. 6,317,376 disclose that a plurality of reference memory cells are used to generate a reference signal. The TMR element, however, has such a characteristic that the resistance value changes in accordance with a voltage applied to the both ends thereof.
FIGS. 17 and 18 illustrate a problem occurring when a plurality of TMR elements are used as reference cells to produce a reference signal.
Referring to FIG. 17, in order to discriminate a memory cell storing xe2x80x9cHxe2x80x9d from a memory cell storing xe2x80x9cL,xe2x80x9d an intermediate value between a current value IH and a current value IL is required as reference current.
Reference cell 871 stores data xe2x80x9cH,xe2x80x9d whereas reference cell 872 stores data xe2x80x9cL.xe2x80x9d A voltage V is applied to the both ends of reference cells 871, 872 connected in parallel, to provide current of IH+IL flowing as reference current Iref. Current with half the magnitude of the reference current is required as the reference value for data discrimination.
Even if the voltage applied to the both ends of the parallely connected reference memory cells 871, 872 is changed from voltage V to xc2xdxc2x7V, reference current Irefa obtained here will not be half the value of IH+IL, as shown in FIG. 18. This is because the voltage applied to both ends of TMR element reduced to xc2xd would change the resistance value of the TMR element. Hence, a current value IHa will not be half the value of IH and current value ILa will not be half the value of current value IL.
FIG. 19 illustrates an example disclosed in U.S. Pat. No. 6,269,040 where a reference signal is produced by applying the same voltage to both ends of a TMR element in each of the reference cell and the memory cell to be read out.
Referring to FIG. 19, a row selection line 903 is selected and bit line 905 is connected to one input of a sense amplifier 901 by a switch SW1 of switches SW1 to SW6. In addition, a bit line 908 is connected to one input of a sense amplifier 902 by switch SW5.
Two reference columns 910, i.e. bit lines 906 and 907, are connected to the other input of sense amplifiers 910, 902 provided in common, by switches SW3, SW4, respectively. Here, the reference cell connected to bit line 906 holds a logic value xe2x80x9cL,xe2x80x9d whereas the reference cell connected to bit line 907 holds a logic value xe2x80x9cH.xe2x80x9d
Then, current flows as an averaged signal of the logic values xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d at the inputs of the sense amplifiers for the reference signal. This allows the logic values of memory cell X1 or memory cell X2 to be determined. The reference cell may be similar to a normal memory cell and may be read out as in the case with the normal memory cell, so that an accurate reference signal can advantageously be output.
In this system, however, two reference cell columns are required for each sub array, so that further reduction of the area occupied by the reference cell is desired. The reference memory cell may be provided outside the array, which may however cause a change in the characteristic depending on the locations of the cells within the memory array depending on variations in processes. This may increase the difference in characteristics between a memory cell and a reference cell, resulting in disadvantageous reading.
An object of the present invention is to provide a non-volatile memory device that can generate accurate reference current for determination while reducing the area on a chip occupied by reference cells.
According to an aspect of the present invention, a non-volatile memory device using a resistance element storing data in accordance with a change in a resistance value includes a memory array. The memory array includes a plurality of bit lines; a plurality of memory cells for storing externally-applied data, a plurality ones of the memory cells being connected to each of the bit lines; and a plurality of reference memory cells for holding a reference value for discriminating data to be read out from the plurality of memory cells, each of the reference memory cells being connected to each of the bit lines. The non-volatile memory device further includes a selection circuit selecting at least one of the plurality of memory cells as a selected cell in accordance with an input address, and selecting at least two of the plurality of reference memory cells connected to a bit line different from a bit line to which the selected cell is connected, as a plurality of selected reference cells corresponding to the selected cell, and a read control circuit performing detecting operation of read data of the selected cell in accordance with current flowing in the whole of the plurality of selected reference cells. The read control circuit equally holds a voltage applied to each of the plurality of selected reference cells and a voltage applied to the selected cell at the detecting operation.
A main advantage of the present invention is, therefore, that the area in a memory array occupied by reference memory cells can be reduced, since only one row of reference memory cells may be sufficient.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.